1. Field of the Invention
The present invention relates to a thin film transistor, a display device using thereof and a method of manufacturing the thin film transistor and the display device.
2. Description of Related Art
Thin film transistors (TFT) are widely used as a transistor for driving pixels in an active matrix liquid crystal display device (AMLCD). Especially an amorphous silicon (a-Si) TFT using an amorphous silicon (Si) film as a semiconductor film of a TFT only requires a few number of manufacturing processes and is easy to increase glass substrate size, thereby achieving high productivity. Therefore, a-Si TFT is the mainstream of TFTs for the present AMLCD. Furthermore, there is an increasing tendency of simplifying panel parts of AMLCD to improve reliability by using a-Si TFT to the peripheral circuit device for driving AMLCD. Moreover, commercial production is proceeding for a-Si TFT AMOLED which uses a-Si TFT for the pixel driving circuit device of an active matrix organic EL display device (AMOLED) in which polycrystalline silicon (p-Si) TFT is mainly used in related art. This realizes a cheap and wide area AMOLED.
In order to further simplify the manufacturing process and improve productivity, an inverted staggered type channel etch (CE) structure is mainly used for a-Si TFT. In the inverted staggered type, a gate electrode is formed over an insulating substrate and a gate insulating film is formed to cover the gate electrode. A silicon film having a source/drain region and a channel region is opposed to the gate electrode with the gate insulating film interposed therebetween over the gate electrode. Moreover, conductive impurities are included in the silicon film and this conductive impurity concentration becomes maximum at the side far from the gate electrode. As The CE structure, a channel region is formed in the manufacturing process by etching to remove the conductive impurity layer formed to the back channel side of the silicon film.
The a-Si TFT with the inverted staggered CE structure has a serious shortcoming if used as a peripheral circuit device for driving AMLCD or a pixel driving circuit device of AMOLED. The shortcoming is that the driving performance of TFT is low and drain current at ON state is not enough to be used as a circuit device. Usually, this shortcoming is made up by increasing a channel width of a TFT, however such expansion in occupation area of a TFT is an interference to higher resolution of AMLCD and AMOLED.
The key factor to low on current of the inverted staggered CE structure a-Si TFT is its low carrier mobility (μeff). In the inverted staggered type a-Si TFT, generally μeff is larger for etch stopper (ES) structure a-Si TFT than CE structure a-Si TFT. However, the inverted staggered ES structure TFT additionally requires photolithography for ES, thus the productivity is low.
As mentioned above, in the manufacturing process of the inverted staggered CE structure TFT, a channel region is formed by etching to remove the conductive impurity layer formed to the back channel side of the silicon film. This exposes the back channel side to the surface and the back channel side is exposed to plasma etching and heat treatment. Therefore, with the inverted staggered CE structure TFT, dangling bond in silicon increases during these processes, thereby leading to deterioration of μeff. A dangling bond means the bonding hand occupied by an electron (unpaired electron) which loses the partner of covalent bond and does not participate in bonding. Accordingly, electrons in dangling bond are unstable. In Japanese Unexamined Patent Application Publications No. 60-136259, 61-46069 and 7-78997, the technique is disclosed to reconstruct a dangling bond generated in silicon by hydrotreating. Moreover, in Japanese Unexamined Patent Application Publication No. 2004-363626, the technique is disclosed to reconstruct a dangling bond generated in silicon by hydrotreating in LTPS-TFT (low-temperature p-Si TFT). Furthermore, Japanese Unexamined Patent Application Publication No. 60-136259, 61-46069, 7-78997 and 2004-363626 are related to a planer type TFT.
For a p-Si TFT, a silicon oxide film is usually used as an insulating film. Especially for a gate insulating film, a silicon oxide film is used, which is formed by Plasma Enhanced Chemical Vapor Deposition (CVD) with TEOS (Tetra Ethyl Ortho Silicate) having high hydrogen concentration as material gas. By covering the silicon oxide film with a cap film such as a silicon nitride film and applying a heat treatment, hydrogen is sufficiently diffused under the cap film and the dangling bond in the silicon is reconstructed.
On the other hand, in Jpn. J. Appl. Phys., Vol. 37 (1998) pp. L112-L114 (T. Sameshima, M. Satoh, K. Sakamoto, A. Hisamatsu, K. Ozaki and K. Saitoh), Jpn. J. Appl. Phys., Vol. 37 (1998) pp. L1030-L1032 (T. Sameshima, M. Satoh, K. Sakamoto, K. Ozaki and K. Saitoh) and Jpn. J. Appl. Phys., Vol. 39 (2000) pp. 2492-2496 (K. Sakamoto and T. Sameshima), dangling bond in a silicon film, a silicon oxide film and an interface between the silicon film and the silicon oxide film is improved in low-temperature (300 to 350 degrees Celsius) annealing in water vapor atmosphere. Jpn. J. Appl. Phys., Vol. 37 (1998) pp. L112-L114 (T. Sameshima, M. Satoh, K. Sakamoto, A. Hisamatsu, K. Ozaki and K. Saitoh) discloses that the dark conductivity of a-Si and low-temperature p-Si decreases and photoconductivity of them increases by low-temperature (350 degrees Celsius) heat treatment in water vapor atmosphere. Jpn. J. Appl. Phys., Vol. 37 (1998) pp. L1030-L1032 (T. Sameshima, M. Satoh, K. Sakamoto, K. Ozaki and K. Saitoh) discloses that μeff of low-temperature p-Si TFT increases and threshold current decreases by high pressure water vapor annealing and atmospheric pressure vapor annealing. Jpn. J. Appl. Phys., Vol. 39 (2000) pp. 2492-2496 (K. Sakamoto and T. Sameshima) discloses that the trap level density of an interface between a silicon film and a silicon oxide film is improved by high pressure water vapor annealing and Si—O bond increases. Moreover, it also discloses that the dangling bond density which is the main factor of the trap level decreases and Si—O bond increases in low-temperature annealing in water vapor atmosphere. Jpn. J. Appl. Phys., Vol. 37 (1998) pp. L112-L114 (T. Sameshima, M. Satoh, K. Sakamoto, A. Hisamatsu, K. Ozaki and K. Saitoh), Jpn. J. Appl. Phys., Vol. 37 (1998) pp. L1030-L1032 (T. Sameshima, M. Satoh, K. Sakamoto, K. Ozaki and K. Saitoh) and Jpn. J. Appl. Phys., Vol. 39 (2000) pp. 2492-2496 (K. Sakamoto and T. Sameshima) suggest that not only hydrogen but moisture contributes greatly to the improvement of dangling bond in a silicon film, a silicon oxide film and an interface between the silicon film and the silicon oxide film, which has been explained in related art.
Moreover, silicon oxide films not only dilute hydrogen from a nitride film but there are silicon oxide films which discharge moisture at the time of annealing. According to Jpn. J. Appl. Phys., Vol. 32 (1993) pp. 1787-1793 (N. Hirashita, S. Tokitoh and H. Uchida), there are three-stage moisture discharge temperature by TDS (Thermal Desorption Mass Spectroscopy) measurement of a silicon oxide film using TEOS as material gas. The first stage is 100 to 200 degrees Celsius, the second stage is 150 to 300 degrees Celsius and the third stage is 350 to 650 degrees Celsius. The moisture discharge in the first and the second stages is by absorbed water in a silicon oxide film using TEOS as material gas. Then the moisture discharge in the third stage is said to be moisture discharge by Si—OH (Jpn. J. Appl. Phys., Vol. 32 (1993) pp. 1787-1793 (N. Hirashita, S. Tokitoh and H. Uchida)).
Usually, in the manufacturing process of the inverted staggered CE structure a-Si TFT, a silicon nitride film is mostly used as an insulating film. When forming a silicon nitride film by plasma CVD, hydrogen plasma occurs at the time of plasma CVD and hydrogen can be introduced. However, the hydrogen amount generated at the time of plasma CVD is not enough to reconstruct a dangling bond in silicon.
There are few examples of an oxide film in a silicon interface in the inverted staggered CE structure TFT of related art. The oxide film over the silicon surface in Japanese Unexamined Patent Application Publication No. 8-172202 is an oxygen plasma oxide film used as a stopper for etching when etching to remove the conductive impurity layer in the manufacturing process of the inverted staggered CE structure TFT. This oxygen plasma oxide film cannot reconstruct the dangling bond in silicon sufficiently.
Japanese Unexamined Patent Application Publications No. 9-298303 and 11-330472 relate to the inverted staggered type ES structure TFT. The silicon oxide film here is used for reducing level density in the interface between the silicon nitride film and the silicon film and the silicon oxide film is not used to reconstruct the dangling bond in silicon. Accordingly, the improvement effect of μeff is low.